MODELING AND VERIFICATION OF PARALLEL DATA PROCESSING AND ACCESS IN RECONFIGURED DEVICES USING PETRI NETWORKS

Abstract

The article presents the results of a comprehensive study devoted to the organization of highly efficient parallelism in the hardware implementation of cryptographic algorithms, which is a critical requirement for modern infocommunication systems with regulated and secure access to users’ personal data. Special attention is paid to increasing throughput and scalability of encryption modules while maintaining strict security guarantees. As a representative cryptographic primitive, the Advanced Encryption Standard (AES) algorithm operating in counter mode (CTR) was selected and analyzed as a streaming workload. The choice of AES-CTR is justified by its inherent block independence, absence of data dependencies between encryption rounds of different blocks, and natural suitability for parallel execution and dynamic scaling of computing resources.

A formalized architectural model of a hardware-based digital stream encryption module is proposed. The model is described using Petri nets, which provide a rigorous and expressive means for representing concurrent processes, synchronization mechanisms, task dispatching, mutual exclusion, and buffering of input data streams. This approach allows the analysis of system behavior under various workloads and configurations, as well as the identification of potential bottlenecks and contention points in parallel execution.

To validate the proposed architectural solutions and assess their practical effectiveness, software prototypes of parallel AES-CTR implementations were developed in C++. Experimental evaluations were conducted to measure execution time, achieved bandwidth, and acceleration factors for different numbers of parallel streams and varying data volumes. The scalability characteristics of the solution were analyzed in detail, demonstrating the efficiency of parallel processing under increasing computational load. In addition, functional testing was performed using real files of different sizes and formats, confirming the correctness, robustness, and practical applicability of the proposed parallel encryption approach. The obtained results substantiate the feasibility of the developed model for high-performance cryptographic hardware systems.