FREQUENCY DIVIDER WITH VARIABLE DIVISION RATIO FOR DIGITAL SYSTEMS BASED ON FPGA 7-TH SERIES OF XILINX

Abstract

Complex computing devices with reconfigurable architectures are widely used in real-time systems where it is necessary to change the operation algorithm. Field Programmable Gate Arrays (FPGAs) are base components for such devices. FPGAs enable to design of computing devices wherein the hardware structure is configured to implement the operation algorithm in the most efficient manner. This approach allows for more effective technical solutions compared to those based on microprocessors and microcontrollers.

When developing such devices on FPGAs, it is necessary to implement a set of synchronization and control signals with frequencies in hundreds or even thousands of times lower than the main clock frequency. Modern FPGAs include a set of Mixed-Mode Clock Manager (MMCM) hardware modules to generate the required set of frequencies. However, the number of MMCMs is limited, and their signals are typically global within the project. Therefore, using MMCMs is not justified when it is necessary to implement a local set of synchronization and control signals within a separate module of a complex project.

The article presents a method for implementing digital counters/dividers with a variable division ratio for systems based on the 7th series of XILINX FPGAs. The method assumes that dividers are implemented using multifunctional Look-Up Tables (LUTs) operating in shift register mode, without employing traditional binary counters/dividers implemented with D flip-flops.

Using a shift register with connected input and output is one of the most effective ways to implement dividers. The length of the register determines the division ratio (N) of such a divider. This solution allows the output signal frequency to be reduced by a factor of N compared to the main clock frequency, while the pulse duration remains the same as the clock signal period.

The divider operates in two modes: 1) division mode; 2) initialization mode. In division mode, the output provides a signal divided by N. The divider switches to initialization mode after a hardware reset or when the user decides to change the division ratio. Unlike well-known solutions, the proposed technical design uses a small Finite State Machine (FSM) to control divider operation in initialization mode. The application of an FSM allows the implementation of a divider with a variable division ratio without the need to update the design.

The obtained results show that the divider requires fewer FPGA hardware resources for implementation compared to traditional binary counters built with D flip-flops. The proposed divider can be used as a base component in the design of programmable dividers/timers. Connecting several dividers in series allows the total division ratio factor to be increased by multiplying the division factors of each divider, achieving a total division factor of 10³–10⁶.

The design of a custom IP-core of a programmable divider/timer supporting of the AXI system bus, will be the next step of researching.