A METHOD FOR INCREASING THE PRODUCTIVITY OF THE AD-CONVERSION BY THE COMBINATION OF BIT-BALANCED AND SIGMA-DELTA ADC

Abstract

The article considers the proposed method of increasing the productivity of analogue-to-digital conversion by combining a bit-balanced ADC with weight redundancy and further AD conversion using a sigma-delta ADC. The essence of this method is analyzed which consists in the fact that the conversion process is carried out in two stages. At the first stage, an analogue signal (voltage or current) is converted into an n-bit code by bitwise approximation. It is noted that the use of weight redundancy can significantly (by an order of magnitude) reduce the equilibration time. It is shown that further increase of the bit depth is expedient to implement by sigma-delta equilibration. This is especially important in the presence of noise and interference. A block diagram of an ADC containing a bit-wise equilibration ADC and a sigma-delta ADC is presented, where the input of the latter is expediently connected to the input bus of the device and to the DAC output of the bit-wise approximation ADC. The rationale for using sigma-delta ADCs is due to their high resolution of ≥ 16 bits. It is also shown that the use of a bit-by-bit ADC at the first stage of the conversion allows the last stage to reduce the amplitude of the undercompensated difference signal by several orders of magnitude, which will allow the sigma-delta ADC to quickly enter the tracking equilibrium mode and obtain the output code at each conversion cycle.

Thus, it is proved that the proposed method of improving the performance of the ADC conversion can significantly increase the coding resolution at the level of 30 binary bits while maintaining the average speed (units and tens of microseconds). Such characteristics of information form converters can be achieved using the modern element base of Analog devices, Burr-brown, National semiconductor, etc.