PHYSICAL FOUNDATIONS AND IMPLEMENTATION METHODS OF P-BITS

Abstract

This article presents a comprehensive overview of the physical principles, hardware architectures, and technological implementations of p-bits — stochastic binary elements that constitute the fundamental building blocks of probabilistic computing systems. P-bits, unlike conventional deterministic logic elements, operate based on controlled randomness, enabling efficient realisation of computational tasks that are inherently probabilistic in nature. The review covers a wide range of key hardware technologies employed in the creation of p-bits, including superparamagnetic magnetic tunnel junctions (s-MTJ), memristors, resistive random-access memory (RRAM), CMOS-based circuits, and field-programmable gate arrays (FPGA). For each of these approaches, the article details the underlying physical operating principles, characteristic parameters, strengths, and inherent limitations, providing a comparative analysis of their suitability for various computational scenarios. Special attention is given to recent advances in the development of experimental prototypes and architectures that integrate multiple p-bits into scalable systems, exploring their potential for large-scale implementation. Examples of contemporary hardware platforms are discussed in the context of practical applications such as stochastic modelling, combinatorial optimisation problems, and inverse computations in machine learning and data analysis. Furthermore, the article examines the future prospects of probabilistic computing, highlighting emerging trends in material science, nanoscale fabrication, and circuit design aimed at improving the performance, energy efficiency, and reliability of p-bit devices. The concluding section addresses open challenges and outlines possible research directions for bridging the gap between current laboratory-scale prototypes and fully functional, commercially viable probabilistic computing platforms.