METHODS OF BUILDING HIGH-PERFORMANCE ADC USING STRUCTURAL AND INFORMATION REDUNDANCY

Abstract

The paper presents the results of research on methods of building high-performance multi-bit (n≥12 bits) ADCs using structural and informational redundancy based on redundant positional computing systems (RPSCs).

The application of structural redundancy is considered on the example of a two-stage parallel-serial ADC. The structural diagram of such an ADC is presented and the principle of its operation, as well as the method of forming the conversion result, are analyzed. The possibility of increasing the bit rate of such ADCs by increasing the number of stages of the device is shown. It was stated that the use of the principle of information redundancy allows to significantly increase the performance of the ADC. It is proposed to significantly increase speed, and, accordingly, productivity, to use a higher level of redundancy, in particular, a calculation system of the "golden" ratio type (=1.62), which allows to increase speed, compared to the binary analogue, by 5 ̶ 8 times. Options for building such ADCs with weight redundancy based on the counting system with bit coefficients [0, 1] and [-1, 1] are given and analyzed. The functioning of such devices is considered. It is indicated that for a further level of productivity, it is expedient to use both informational and combined structural methods, in particular, in the ADC of bit-by-bit tracking balancing with weight redundancy. The peculiarity of such a device is that after entering the monitoring mode, the source code is formed in only one cycle, that is, the performance of the proposed ADC approaches the reading ADC and, even more, due to the increase in the number of digits of the conversion results. The structural diagram of the ADC of bit-by-bit tracking balancing with weight redundancy, the balancing diagram, as well as the graph-scheme of the functioning algorithm are given.