NOISE IMMUNITY ANALYSIS OF PROTECTED 5G COMMUNICATION SYSTEM WITH POLAR CODING
DOI:
https://doi.org/10.31891/2219-9365-2023-75-18Keywords:
communication system, polar coder, channel polarization, successive cancellation decoder, bit error rate, 5GAbstract
The transmission of information in mobile telecommunications through a communication channel is accompanied by the occurrence of errors. Polar codes are a family of codes that achieve the bandwidth of symmetric channels without memory. Polar codes provide good error correction at low decoding complexity for practical block lengths when combined with more sophisticated decoding algorithms. This made it possible to use polar codes in the 5G wireless communication standard. The purpose of the work is to study the communication system with the serial exclusion decoder, the implementation of this decoder on the FPGA, and the determination of the bit error rate using mathematical modeling in the MATLAB environment. Polar coding performs the operation of polarization of the communication channel. Channel polarization is an operation by which a polarized set of N channels is created from N independent copies of a given channel W, the bandwidth of which tends to zero or unity. The basic algorithm of polar decoding is a sequential elimination algorithm. The recovered data must be sorted similarly to the input data, so the encoder input and decoder output must mirror each other. Each stage consists of N/2 nodes F and G connected together in a structure resembling a fast Fourier transform. Node G is a bitwise conditional adder/subtractor representing the modulo 2 partial sums of the previously evaluated bits. The rule for calculating partial sums is based on the structure that copies the corresponding polar coder. The sequential elimination decoding algorithm consists of two tasks, the first of which runs sequentially from the input stage to the output stage to compute the final LLR and make a hard decision. The second task recursively executes the predecessor nodes to backpropagate the decoded bits from the decoder output to the corresponding predecessor stage. The polar encoder and decoder are implemented on the FPGA System-on-Chip (SoC) Intel DE10-Standard Development Kit. A study of the number of bit error rate from the signal-to-noise ratio for a communication system with BPSK modulation and different code block lengths, cyclic redundant code and bit reversal, different sizes of the sequential exclusion list and different code rates was carried out.